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Other titre : Hardware implementation of a spiking neural network for fast synchronization

dc.contributor.advisorRouat, Jeanfr
dc.contributor.advisorMailhot, Frédéricfr
dc.contributor.advisorSchrauwen, Benjaminfr
dc.contributor.authorCaron, Louis-Charlesfr
dc.date.accessioned2014-05-14T19:56:49Z
dc.date.available2014-05-14T19:56:49Z
dc.date.created2011fr
dc.date.issued2011fr
dc.identifier.isbn9780494836866fr
dc.identifier.urihttp://savoirs.usherbrooke.ca/handle/11143/1603
dc.description.abstractIn this master thesis, we present two different hardware implementations of the Oscillatory Dynamic Link Matcher (ODLM). The ODLM is an algorithm which uses the synchronization in a network of spiking neurons to realize different signal processing tasks. The main objective of this work is to identify the key design choices leading to the efficient implementation of an embedded version of the ODLM. The resulting systems have been tested with image segmentation and image matching tasks. The first system is bit-slice and time-driven. The state of the whole network is updated at regular time intervals. The system uses a bit-slice architecture with a large number of processing elements. Each processing element, or slice, implements one neuron of the network and takes the form of a column on the hardware. The columns are placed side by side and they are locally connected to their 2 neighbors. This local hardware connection scheme makes the system scalable, which means that columns can be easily added to increase the capacity of the system. Each column consists of a weight vector, a synapse model unit and a membrane model unit. The system can implement any network topology, making it very flexible. The function governing the time evolution of the neurons' membrane potential is approximated by a piece-wise linear function to reduce the amount of logical resources required. With this system, a fully-connected network of 648 neurons can be implemented on a Virtex-5 Xilinx XC5VSX5OT FPGA clocked at 100 MHz. The system is designed to process simultaneous spikes in parallel, reaching a maximum processing speed of 6 Mspikes/s. It can segment a 23×23 pixel image in 2 seconds and match two pre-segmented 90×30 pixel images in 550 ms. The second system is event-driven. A single processing element sequentially processes the spikes. This processing element is a 5-stage pipeline which can process an average of 1 synapse per 7 clock cycles. The synaptic weights are not stored in memory in this system, they are computed on-the-fly as spikes are processed. The topology of the network is also resolved during operation, and the system supports various regular topologies like 8-neighbor and fully-connected. The membrane potential time evolution function is computed with high precision using a look-up table. On the Virtex-5 FPGA, a network of 65 536 neurons can be implemented and a 406×158 pixel image can be segmented in 200 ms. The FPGA can be clocked at 100 MHz. Most of the design choices made for the second system are well adapted to the hardware implementation of the ODLM. In the original ODLM, the weight values do not change over time and usually depend on a single variable. It is therefore beneficial to compute the weights on the fly rather than saving them in a huge memory bank. The event-driven approach is a very efficient strategy. It reduces the amount of computations required to run the network and the amount of data moved in and out of memory. Finally, the precise computation of the neurons' membrane potential increases the convergence speed of the network.fr
dc.language.isoengfr
dc.publisherUniversité de Sherbrookefr
dc.rights© Louis-Charles Caronfr
dc.subjectTraitement d'imagesfr
dc.subjectSystème embarquéfr
dc.subjectSynchronisationfr
dc.subjectRéseau de neurones à déchargesfr
dc.titleImplémentation matérielle d'un réseau de neurones à décharges pour synchronisation rapidefr
dc.title.alternativeHardware implementation of a spiking neural network for fast synchronizationfr
dc.typeMémoirefr
tme.degree.disciplineGénie électriquefr
tme.degree.grantorFaculté de géniefr
tme.degree.levelMaîtrisefr
tme.degree.nameM. Sc. A.fr


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